The following document is an attempt to describe the state of DSS 3 at the present time. There are several hardware components and a great deal of software associated with each component. There is much work yet to be done of course, but all the major components are in place with some sort of prototype which can be improved. The improvements will be enhanced with feedback from users.

A block diagram of the project as it stands now looks like this:

The PC44 and PC32 cards are mounted inside a host computer and are programmed via the ISA bus. The 25 bit DAC is an option for the PC44. The PC44 card does have two 16 bit DAC’s as well as two 16 bit ADC’s. Unfortunatly, there are only three channels which can be run independently, so two devices must run at the same rate if all four are to be used.

The PC32 card is the time base for the entire system. It has a 64 Mhz clock which is used to derive all input and output times. Connected to the PC32 is an Interface card which allows it to control the rate generators and to collect data from the I/O interface. There will be four rate generators which can run indepenedently, but their master clock is derived from the PC32 card.

At present the input/output for levels is clocked at 1 Mhz. The levels are connected via the I/O interface board. Up to 32 channels can be controlled (on or off) and up to 32 channels can be monitored for on or off states. The I/O interface card has not been constructed, it will be designed to convert rising edges to levels which can be cleared once read in. This interface is similar to DSS 2. For the moment, using levels for inputs doubles the amount of data but allows software in general to be written for collecting data. Post processing can reduce this to make the data look like DSS 2 UET data.

Each processor in this system requires a different program. Because each processor is different they all require different assemblers as well. The PC44 and PC32 cards can be individually programmed and each step of the code can be monitored using a software/hardware tool called Code Composer. Only one processor at a time can be monitored because the hardware is different between the PC32 and PC44. This is not too much of a problem since each processor is relatively independent in its tasks.

The rate generator card is composed of 5 processors. Four of the processors are the rate generators and one processor is the controller which connects the board to the PC32 Interface card. A block diagram of the rate generator is given below.

The PIC microcontroller takes commands from the PC32 and boots each rate generator processor. Each rate generator runs with a starting phase and fixed increment of 48 bits. The update rate is 16 Mhz. The least significant bit amounts to a frequency of 10^-7 Hz and the most significant bit will force a change of state at 8 Mhz. The output of each rate generator can be started and stopped with an external TTL signal. Once booted by the PIC controller, a rate generator processor will wait until the start line goes high. Once it does, only a PIC reset or the stop line going low will halt the output. The high to low transition on the stop line restarts the processor and it again waits for the start line to go high before generating output. The starting phase is re-initialized and the rate generator duplicates the previous timing for every stop/start event.

The booting process takes place over a serial line. This requires 165 milliseconds to complete for each processor, so setting up the entire board takes a bit more than 3/4 of a second. Once set up, the start and stop lines will respond within 40 nanoseconds of the proper transition. Changing rates or starting phase requires rebooting a rate generator processor. Once started, a rate generator has instantaneous response.

The software which runs on the DSP rate generators is hand coded and burned into the ROM of the PIC controller. The software which runs on the PIC controller is assembled using the tools designed to assemble and burn its on board ROM. The counter and phase are variables stored in RAM on the PIC controller, and these values are transfered from the PC32. The boot process for each DSP processor requires commands from the PC32 to set the phase, the clock rate, and then a specific boot command. The PIC then puts the phase and clock rate into the correct portion of the instruction stream and transfers the complete boot code to the rate generator processor. Once booted, the PIC will ignore the DSP rate generator until commanded to boot it again.

Testing of the entire system will begin this week. Software to get rates and phases from the user keyboard to the rate generator needs to be written and connections between the PC32 level control, the rate generators and PC44 also need to be made and tested. Forward ho!